1. Field of the Invention
The present subject matter generally relates to the field of fabrication of integrated circuits, and, more particularly, to a structure and a method for determining an overlay accuracy, that is, an alignment accuracy, between two layers of a multi-layered device.
2. Description of the Related Art
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities, there has been and continues to be efforts towards scaling down device dimensions. Hence, the fabrication of microstructures, such as integrated circuits, requires tiny regions of precisely controlled size to be formed in a material layer over an appropriate substrate, such as a silicon substrate, a silicon-on-insulator (SOI) substrate or other suitable carrier materials. These tiny regions of precisely controlled size are generated by patterning the material layer by performing photolithography, etch, implantation, deposition, oxidation processes and the like. Typically, at least in a certain stage of the patterning process, a mask layer may be formed over the material layer to be treated to define the tiny regions. Generally, a mask layer may consist of or may be formed by means of a layer of photoresist that is patterned by a lithographic process. During the lithographic process, the resist may be spin-coated onto the wafer surface and then selectively exposed to ultraviolet radiation through a corresponding lithography mask, such as a reticle, thereby imaging the reticle pattern into the resist layer to form a latent image therein. After developing the photoresist, depending on the type of resist, positive resist or negative resist, the exposed portions or the non-exposed portions are removed to form the required pattern in the layer of photoresist. Since the dimensions of the patterns in sophisticated integrated circuits are steadily decreasing, the equipment used for patterning the device features have to meet very stringent requirements with regard to resolution and overlay accuracy, i.e., the alignment accuracy of the individual layers with respect to each other, of the involved fabrication processes. In this respect, resolution is considered as a measure for specifying the consistent ability to print minimum size images under conditions of predefined manufacturing variations. One important factor in improving the resolution is represented by the lithographic process, in which a pattern contained in the photo mask or reticle is optically transferred to the substrate via an optical imaging system. Therefore, great efforts are made to steadily improve optical properties of the lithographic system, such as numerical aperture, depth of focus and wavelength of the light source used. The quality of the lithographic systems and processes is extremely important in creating very small feature sizes.
Of at least comparable importance, however, is the accuracy with which an image can be positioned on the surface of the substrate. Typically, microstructures such as integrated circuits are fabricated by sequentially patterning material layers wherein features on successive material layers bear a spatial relationship to each other. Each pattern formed in subsequent material layers has to be aligned to a pattern formed in the previously patterned material layer within specified registration tolerances. Deviations from an ideal registration are caused by, for example, a variation of a photoresist image on the substrate due to non-uniformities in such parameters as resist thickness, temperature, exposure dose, time and developing conditions. Furthermore, non-uniformity of the etch processes may also lead to variations in the etched features. In addition, there exists an uncertainty in overlaying the image of the pattern of the current material layer to the etched or otherwise defined pattern of the previously formed material layer while photolithographically transferring the image of the photo mask onto the substrate. Several factors contribute to the inability of the imaging system to perfectly overlay two layers, such as imperfections within a set of masks, temperature differences at the different times of exposure and limited registration capability of the alignment tool. As a result, the dominant criteria for determining the minimum feature size that may finally be obtained are the resolution for creating features in the individual substrate layers and the total overlay error to which the above-explained factors, in particular the lithographic processes, contribute.
Therefore, it is essential to steadily monitor the resolution, i.e., the capability of reliably and reproducibly creating the minimum feature size, also referred to as critical dimension (CD), within a specific material layer, and to steadily determine the overlay accuracy of patterns of material layers that have been successively formed and that have to be aligned to each other.
Conventional overlay metrology systems facilitate determining whether two layers lie within the acceptable tolerances. There are two main functions of overlay metrology regarding fabrication of integrated circuits: monitoring performance of lithographic alignment procedures and assisting in setup of a lithography process. For example, overlay metrology may be utilized with a sample wafer to assess overlay performance of a wafer lot. Moreover, overlay measurements may be utilized to optimally configure a stepper system prior to operation, and may later be employed to maintain optimal stepper performance via periodic overlay evaluation. In overlay metrology, two independent structures, that is, one structure in each layer to be printed, are formed by the specified manufacturing processes. The overlay error may be determined by measuring the displacement between the centers of symmetry of the two independent structures. As independent structures, frequently so-called box-in-box marks are used which are concentrically patterned in each of the layers. The displacement of the structures may be measured in units of pixels of a charge coupled device (CCD) onto which the concentric alignment marks are imaged during the measuring process.
For ever-decreasing feature sizes of microstructures, however, the detection of a displacement and thus the quantification of an overlay error between both overlay marks on the basis of edge finding routines may no longer be adequate. Therefore, recently, so-called advanced imaging metrology (AIM) marks are increasingly used to enhance overlay metrology reliability. AIM marks exhibit a periodic structure, thereby enabling utilization of highly powerful metrology techniques. Hence, increased performance of the overlay metrology may be obtained by using periodic overlay marks. With decreasing feature sizes, however, a discrepancy between overlay characteristics within a single die and the significant larger overlay marks may be observed, thereby rendering measuring data obtained from the target less reliable. The overlay marks are typically located in the scribe line of the substrate, i.e., in a region between dies empty of circuitry. One reason for the discrepancy between overlay characteristics within a single die resides in the fact that the lithography tool may image fine structures, as are typically found within a die, such as gate electrodes, shallow trench isolation (STI) structures and the like, in a different manner compared to relatively large structures, which are typically used to form overlay marks. This pattern and size-dependent phenomenon is called pattern placement error (PPE). Consequently, the pattern placement error has to be quantified in order to correct the results of the overlay measurements obtained from the overlay marks within a scribe line with respect to the contribution to actual microstructural features within the die. The pattern placement error may be conveniently measured by so-called simultaneous AIM overlay marks, as will be described in more detail below.
An overlay measurement structure in the form of an AIM mark comprises a periodic structure which may enable the measurement of an overlay error in at least two independent directions. The overlay measurement structure may be formed according to the following process flow. A first periodic structure may be formed in a corresponding device layer, such as a layer receiving STI trenches. It should be appreciated that a selection of respective sequences of material layers is arbitrary and the principles of the formation of the overlay measurement structure may be correspondingly applied to any front end or back end process sequence involving a photolithography step for patterning a further material layer on top of one or more previous layers. A pattern according to the first periodic structure may be imaged by photolithography into a corresponding resist layer that is formed above the substrate under consideration. After the development of the resist layer, a corresponding well-approved sequence of manufacturing steps including anisotropic etch techniques, deposition techniques, chemical mechanical polishing (CMP) and the like may be performed in order to form the corresponding patterns and also the (first) periodic structures. Thereafter, a process sequence may be performed for forming microstructure features of a second layer on the previously patterned layer, such as gate electrode structures, polysilicon lines and the like. Hence, a plurality of well-established oxidation and deposition processes may be carried out, such as the formation of a thin gate insulation layer and the subsequent deposition of a gate electrode material and the like, followed by a further photolithography process for patterning the structure, thereby simultaneously forming a second periodic structure. As previously pointed out, the individual lines and spaces of the first and second periodic structures may not be formed in accordance with the same design rules, but may be patterned in accordance with metrology requirements so as to enhance the detection of any offset between the first and second periodic structures. Thus, the pitch of the first and second periodic structures may be significantly larger compared to any critical dimension of actual device features formed within the die regions. Consequently, an overlay accuracy with respect to the x- and y-directions may be estimated with moderately high precision for the overlay measurement structure itself, but may not permit a precise estimation of the overlay accuracy within actual die regions having formed therein structural features of significantly less critical dimensions compared to dimensions in the overlying measurement structure. Therefore, in addition to the overlay structure, the so-called simultaneous AIM overlay marks are frequently used, in which at least some of the features of the periodic structures contain a fine structure formed in accordance with the respective design rules for actual device features in the die regions.
As previously explained, due to the pattern placement error, a corresponding shift may be detected in the form of an apparent overlay error, and this measure may be used for assessing the contribution of the pattern placement error within a die region to obtain a measure for correcting the actual overlay error between two different device layers measured by the overlay measurement structure. Thus, during the measurement of sophisticated micro-structural devices, at least two overlay measurement structures have to be provided.
The positioning of the overlay measurement structure in the scribe lines of a wafer is based on the assumption of an overlay model with linear field dependence. However, recent studies have indicated that the discrepancies from field linearity may no longer be negligible for sophisticated overlay control requirements, e.g., at 65 nm technology. For example, scanner lens distortion differences and reticle registration are known as major contributors to intrafield overlay errors. Therefore, for sophisticated applications, it may be necessary to insert design-rule-like metrology structures into locations other than the scribe lines. Since standard size overlay structures are difficult to insert in the chip region and are not representative of the circuit pattern, overlay metrology targets of reduced size, so-called micro targets, appear to be appropriate. For example, the feasibility of measuring overlay using small targets of size between 1×1 μm and 3×3 μm total size has been demonstrated. The image asymmetry is used to measure the overlay error. With no noise in the signal, the response is linear, but noise causes the response of the image symmetry as a function of the overlay error to tail off for small overlay offsets. Therefore, it has been proposed to program an offset into the design of the targets so that the symmetry is always in the linear region of the response curve. Using more than one target, e.g., a group of three or four targets, with different programmed offsets of, e.g., 30 nm, 50 nm and 70 nm, allows checking of the linearity and estimating the robustness of the measurement.
FIG. 1A shows the layout of a single conventional micro target 100 of the so-called box in frame type. The target 100 comprises a first structure 101 which is formed in a reference layer and is generally frame-shaped. Within the first structure 101 is formed a second structure 102 which is generally box-shaped and is formed in a resist layer located above the reference layer. Further indicated in FIG. 1A is the left-side distance Gx1 between the first structure 101 and the second structure 102, as well as the right-side distance Gx2 between the two structures 101, 102 as well as the lower distance Gy1 and the upper distance Gy2 between the two structures 101, 102. As mentioned before, the two structures 101, 102 are not arranged symmetrically, but with a programmed offset. Having an offset Dx in x-direction, the right-side distance Gx2 and the left-side distance Gx1 is given by the following equations:Gx1=Gx0+Dx Gx2=Gx0−Dx wherein Gx0 is the distance between the two structures without offset, i.e., in a configuration where the left-side distance equals the right-side distance. It should be mentioned that the gaps between the two structures, i.e., the left-side distance as well as the right-side distance, are smaller than the resolution of the measurement device. Hence, with the structure shown in FIG. 1A, no edge detection algorithm, but rather an asymmetry measurement, is performed.
Further, having a programmed offset DY in y-direction, the lower distance Gy1 and the upper distance Gy2 is given by the following equations:Gy1=Gy0+DY Gy2=Gy1−DY wherein Gy0 is the distance between the two structures without offset, i.e., in a configuration where the lower distance equals the upper distance.
The overall dimension S of the target 100 shown in FIG. 1A is 3 μm. The width W1 of bars forming the first substructure 101 is 250 nm. The distance Gx0 and Gy0 is 150 nm.
FIG. 1B shows an overlay target assembly 103 having four targets with different programmed offsets. A first target 100A has offsets DX=DY=50 nm. A second target 100B has offsets DX=DY=70 nm. A third target 100C has offsets DX=DY=30 nm, and a fourth target 100D has offsets equal to the offsets of the first target, that is, DX=DY=50 nm. The target assembly 103 is located in a chip region 104. The distance among the targets 100A, 100B, 100C, 100D, as well as the distance between the targets 100A, 100B, 100C, 100D and the chip region 104, are of a certain magnitude D, e.g., D=2 μm. FIG. 1C shows the offset vectors OV1, OV2, OV3, OV4 of the targets 100A, 100B, 100C, 100D. FIG. 1D shows the target assembly 103 in a configuration after a 90 degree rotation compared to the configuration of FIG. 1C. FIG. 1E shows the target assembly 103 of FIG. 1C in a vertically flipped configuration. Usually, a metrology tool used to measure the overlay measures the wafer in only one predefined orientation. Therefore, the measurement recipe has to be adopted for target assemblies which have been rotated or mirrored in the layout, assuming the metrology tool software is flexible enough to handle targets with different directions of the offset vectors.
The present disclosure is directed to various methods and systems that may avoid, or at least reduce, the effects of one or more of the problems identified above.